Co-­Design for Extreme Scale Computing through Runtime Technologies

Thomas Sterling
Intelligent Systems Engineering Department, Professor
Center for Research in Extreme Scale Technologies Indiana University, Director

Abstract
As HPC enters the 100-­Petaflops era with the introduction of the TaiHuLight computer in China, the co-­design of algorithms, hardware architecture, and enabling system software is becoming imperative. The recent generations of systems has exemplified what has been convenient for hardware technologies for maximum flops and reduction of energy, but not application execution efficiency or user productivity. This is particularly true for those problems that require strong scaling or have significant dynamic components. Runtime system software offer an opportunity to address these and other challenges but suffer from overhead costs that hinder their effectiveness, at least for some problems requiring exploitation of near fine-­grain parallelism. Co-­design of system hardware and software architecture with dynamic adaptive application requirements may drive advances of future classes of scalable systems for extreme scale. This presentation will describe the challenges and the gaps between system architecture and dynamic execution that may be bridged through advances in algorithms, runtime software, and hardware architecture design. Results from recent research with the HPX-­5 runtime software system and consideration of investigation of FPGA runtime hardware support will be discussed and conclusions derived in support of advanced co-­design principles. Questions are welcome from the audience throughout the presentation.

Brief Biography Dr. Thomas Sterling holds the position of Professor of Informatics and Computing at the Indiana University (IU) School of Informatics and Computing Department of Intelligent Systems Engineering (ISE) as well as serves as Director of the IU Center for Research in Extreme Scale Technologies (CREST). Since receiving his Ph.D from MIT in 1984 as a Hertz Fellow, Dr. Sterling has engaged in applied research in parallel computing system structures, semantics, and operation in industry, government labs, and academia. Dr. Sterling is best known as the "father of Beowulf" for his pioneering research in commodity/Linux cluster computing for which he shared the Gordon Bell Prize in 1997. He led the HTMT Project sponsored by multiple agencies to explore advanced technologies and their implication for high-end computer system architectures. Other research projects in which he contributed included the DARPA DIVA PIM architecture project with USC-ISI, the DARPA HPCS program sponsored Cray-led Cascade Petaflops architecture, and the Gilgamesh high-density computing project at NASA JPL. Sterling is currently involved in research associated with the innovative ParalleX execution model for extreme scale computing to establish the foundation principles guiding the development of future generation Exascale computing systems. ParalleX is currently the conceptual centerpiece of the XPRESS roject as part of the DOE X-stack program and has been demonstrated via the proof-of-concept HPX-5 runtime system software. Dr. Sterling is the co-author of six books and holds six patents. He was the recipient of the 2013 Vanguard Award and is a Fellow of the AAAS. He is also co-guest editor with Bill Gropp of the HPCwire Exascale Edition.